Surfaces of microelectronic materials such as semiconductors, dielectrics, and metals (often as thin films on a substrate) are generally planarized after their fabrication. The close proximity of microelectronic components, either as multiple layers or as interacting and interconnected subcomponents, requires a high degree of uniformity of the surface. Advances in semiconductor technology have seen the advent of very large scale integration (VLSI) and ultra large scale integration (ULSI) circuits, resulting in the integration of very many more devices in smaller areas on a semiconductor substrate.
The greater device densities require greater degrees of planarity to permit the higher resolution lithographic processes required to form the greater number of devices having smaller features as incorporated in current designs. That is, as successive generations of improvements in semiconductor fabrication are implemented, the tolerance for scratches, erosion, contamination, or other imperfections in the smoothed surface becomes smaller.
One such method of planarization is by chemical mechanical polishing (CMP). CMP, though, is limited because the physical polish often generates scratches, erosion, or other surface defects on the wafer surface. Additionally, the polish rate depends upon the pattern density factor; thus the longer the polish, the worse the uniformity. This non-uniformity of the surface is not within the acceptable tolerances for processing the very thin wire levels of emerging fabrication methods. Also, for fatwire levels, a thick CMP hard mask is often required in the film stack to be sure that some hard mask remains after CMP, if desired.
FIG. 1 shows a graph of the line resistance distribution of multiple chips on twelve wafers—each chip has nested lines with widths of 2.5 μm, 6 μm, 15 μm, and 25 μm, and having 50% pattern density—formed using a conventional CMP process. Along the x-axis are the wafer IDs, and along the y-axis is the line resistance in Ohms. As will be appreciated by one skilled in the art, it is desirable to have uniformity of resistance across the wafer in order to optimize performance. The four different lines on the graph show the resistance varies considerably across each wafer.
Thus, it is desirable to achieve a more planar and smoothed surface, with extremely uniform line resistance across the wafer, even when the surface includes complex structures.